In the manufacture of microelectronic circuits, interconnect structures may be formed on a substrate using a dual damascene process, for example. Such a process may include trench and via openings being formed in an interlayer dielectric (ILD) material, which are then filled with a conductive material, such as copper, for example. A barrier layer may then be formed on the conductive material and on the ILD, which may act as an etch stop/barrier layer during further processing, for example.